This invention relates to an image synthesizing device with which an NTSC or other such interlaced image can be synthesized and displayed in full, magnified, or reduced scale in any region of a VCA or other such non-interlaced image.
An interlaced image of the NTSC system, such as a CCD camera, has odd-numbered fields and even-numbered fields, and one frame (one screen) of image is made up of odd-numbered field images and even-numbered field images. Image scanning is performed alternately for the odd-numbered fields and even-numbered fields in field units, and one screen of image is displayed in two scans.
In contrast, with non-interlaced scanning such as VGA, there is no skipping as above, and one screen is displayed in a single scan, with the displayed image having less flicker than an interlaced scan.
Thus, since there are two different scanning methods for displaying, numerous techniques have been proposed in the past for converting interlaced signals into non-interlaced signals and displaying these in part of a non-interlaced display screen or over the entire region.
One such prior art is Japanese Patent Application Laid-Open No. 5-114026. With this prior art, there is a main image memory that holds main image data (non-interlaced signals), and a sub-image memory of the same capacity as the main image memory that stores sub-image data (interlaced signals) at an address corresponding to this frame memory. When part of the region of the sub-image stored in the sub-image memory is to be synthesized and displayed in part of the main image display region, the sub-image is read out from the sub-image memory when the scanning address of the sub-image memory becomes a specific address corresponding to the synthesis and display region, and when the scanning address of the main image becomes the address at which the sub-image is to be displayed, the display data outputted to the CRT display is switched to the sub-image data that has been read out from the main image data, thereby synthesizing the sub-image data on the main image screen.
Specifically, with this prior art, a sub-image memory of the same capacity as the main image memory capable of storing all sub-images is readied, and the data read-out timing from this sub-image memory is controlled so as to synthesize part of the sub-image on the main image display screen.
Because this prior art is thus provided with both a frame memory for storing main image data and an image memory for storing sub-image data of the same memory capacity as this frame memory, twice the frame memory capacity is required. Consequently, the memory mounting surface area is larger when the circuit is configured, making the overall device larger more expensive.
Another problem with this prior art is that when the sub-image is reduced or magnified in scale, the scale factor is restricted to powers of two, such as xe2x80x9c1/2mxe2x80x9d or xe2x80x9c2m,xe2x80x9d so the scale factor cannot be set in any way desired, which means that this approach is unsatisfactory when the goal is to reduce or magnify a sub-screen precisely to the desired size.
Also, with this prior art, the sub-image memory stores data by an address system in which the data for each pixel is in a one-to-one correspondence with the X-Y address of the CRT display device. Specifically, if the CRT display device is 640 dots wide by 480 dots high, and a one-dot image is one byte, then the sub-image data is stored in memory space as shown in FIG. 10.
Since 640 dots of image data corresponds to 640 bytes, each horizontal synchronous scanning line corresponds to 640 bytes out of the 1024 bytes made up of the lower 10 bits of the memory address. Also, since 480 lines are required in the vertical direction, 480 of the upper 9 bits of the address (512) end up being allocated.
However, with a sub-image memory configured in this way, an area A occupied by the remaining 384 bytes for every horizontal synchronous scanning line of the 480 lines, and an area B occupied by the remaining 32 lines within the upper address space of the 512 lines are unused, so that a number of memories greater than the required memory capacity are required, which is disadvantageous in terms of both cost and mounting surface area.
The present invention was conceived in light of the above problems, and an object thereof is to provide an image synthesizing device with which the image data memory capacity needed for synthesis of main images and sub-images can be decreased, and the reduction or magnification scale factor of the sub-images can be set as desired.
Another object of the present invention is to provide an image conversion device and an image conversion method with which costs can be lowered by allowing non-interlaced signals to be converted into non-interlaced signals using a single frame memory.
Yet another object of the present invention is to provide an image synthesizing device with which costs can be lowered by allowing a specific extraction region of an interlaced scan sub-image to be synthesized and displayed in a specific display region on the display screen on which a non-interlaced scan main image is displayed, using a single serial access memory.
The first invention is an image synthesizing device with which a specific display region P of a sub-image is synthesized and displayed within a specific display region Q of a main image displayed on a display, comprising: a frame memory that continuously stores, in an inputted order, only that data out of sub-image data that is within the display region P to be synthesized, and then reads out the stored sub-image data in the inputted order when a scanning address of the main image data is an address corresponding to the display region Q of the main image; and a selector that inputs the main image data displayed on the display and the sub-image data sequentially read out from the frame memory, and switches a selected channel from this main image data to the sub-image data and outputs it to the display, so that this sub-image data is displayed, when the scanning address of the main image data is an address corresponding to the display region Q of the main image.
Once the scanning address corresponds to the display region in which the sub-image is to be synthesized at the time of sub-image input, the sub-image data is written continuously to the frame memory in the order in which it was inputted, after which the sub-image data is continuously read out from the frame memory in this input order corresponding to the display address when the main image data is displayed in the region Q where the main image is synthesized and displayed, and the main image data is switched to this read sub-image data and displayed on the display, which results in the sub-image being displayed in full scale. In this case, the sub-image may be either interlaced or non-interlaced. Thus, with this invention of claim 1, the sub-images are stored in the continuous address space of the frame memory, so the capacity of the frame memory can be decreased.
The second invention is an image synthesizing device with which a specific display region P of a sub-image is synthesized and displayed within a specific display region Q of a main image displayed on a display, comprising: a first frame memory that continuously stores, in an inputted order, data of odd-numbered fields within the display region P to be synthesized out of interlaced sub-image data, and then reads out the stored sub-image data in the inputted order when a scanning address of the main image data is an address of an odd-numbered line corresponding to the display region Q of the main image; a second frame memory that continuously stores, in the inputted order, data of even-numbered fields within the display region P to be synthesized out of the interlaced sub-image data, and then reads out the stored sub-image data in the inputted order when the scanning address of the main image data is an address of an even-numbered line corresponding to the display region Q of the main image; and a selector that inputs the main image data displayed on the display and the sub-image data sequentially read out from the first frame memory or the second frame memory, and switches a selected channel from this main image data to the sub-image data and outputs it to the display, so that this sub-image data is displayed in full scale, when the scanning address of the main image data is an address corresponding to the display region Q of the main image.
Once the scanning address corresponds to the display region in which the sub-image is to be synthesized at the time of sub-image input, the sub-image data of odd-numbered fields is continuously written to the first frame memory (FIFO serial memory) in the inputted order, and the sub-image data of even-numbered fields is continuously written to the second frame memory (FIFO serial memory) in the inputted order. After this, when the main image data is displayed in the synthesis and display region Q, the sub-image data is continuously read out in the input order from the first frame memory for odd-numbered lines or from the second frame memory for even-numbered lines according to the display address, and the main image data is switched to this read sub-image data and displayed on the display. As a result, an interlaced sub-image is synthesized in full scale and displayed in the display region Q of the main image. Therefore, only the sub-image data to be synthesized is stored in the frame memory, and at the time of synthesis the main image data is switched to this stored sub-image data, so the capacity of the frame memory can be decreased.
The third invention is the image synthesizing device according to first or second invention, wherein, when the display region P of the sub-image is reduced to a specific scale factor and synthesized and displayed in the display region Q of the main image, the frame memory thins the lines in a vertical direction to a specific scale factor when the scanning address of the sub-image data at a time of sub-image data input corresponds to the display region P, and stores the sub-image data which have been inputted after being horizontally thinned out to the specific scale factor when a scanning address in the horizontal direction corresponds to the display region P for each of these thinned-out lines, after which the thinned-out and stored sub-image data is continuously read out in the order of the input when the scanning address of the main image data corresponds to the display region Q of the main image.
When the display region P of the sub-image is reduced to a specific scale factor and synthesized and displayed in the display region Q of the main image, the lines in the vertical direction are thinned out to the specific scale factor only for data corresponding to the display region P of the sub-image data, and each of these thinned-out lines is thinned out to the specific scale factor in the horizontal direction and continuously written to the frame memory, after which, when the main image data synthesis and display region is displayed, the stored sub-image data is read out from the frame memory in the input order, and the main image data is switched to this read sub-image data and displayed, so that the sub-image is synthesized and displayed in reduced scale. Here, since only the sub-image data to be synthesized is reduced to the desired scale factor and stored in the frame memory, the capacity of the frame memory can be decreased, and since reduction to any scale factor is possible, the scale factor required by the user can be achieved.
The fourth invention is the image synthesizing device according to first or second invention wherein a line buffer FIFO is provided with which, after the sub-image data read from the frame memory has been inputted and then stored in the order of this input, this stored sub-image data is read out in the order of the input; when the display region P of the sub-image is magnified to a specific scale factor and synthesized and displayed in the display region Q of the main image, the frame memory continuously stores only that data out of the sub-image data that is within the display region P in the inputted order, after which one line of data out of the stored sub-image data is read out at a cycle reduced to the specific scale factor with respect to a frequency of a horizontal dot clock of the main image one line at a time for a specific number of lines corresponding to the specific scale factor when the scanning address of the main image data corresponds to the display region Q of the main image; and the line buffer FIFO stores this one line of read sub-image data synchronously with the horizontal dot clock of the main image in the inputted order, after which the stored one line of sub-image data is repeatedly outputted for each line in the input order for the remaining lines of the specific lines corresponding to the specific scale factor of the display region Q of the main image data.
Only that data corresponding to the region in which the sub-image data is to be synthesized is continuously written to the frame memory in input order, and then when the synthesis and display region of the main image data is displayed, the main image data is switched so that the stored sub-image data is synthesized and displayed while being magnified horizontally and vertically as follows. The display is magnified horizontally by reading out from the frame memory one line of the stored sub-image data at a cycle reduced to a specific magnification factor for the frequency of the horizontal synchronization signal of the main image one line at a time for a specific number of lines corresponding to the above-mentioned magnification factor. Along with this, one line of this magnified sub-image data is written to the line buffer FIFO. For the rest of the above-mentioned specific number of lines, the sub-image stored in this line buffer FIFO is continuously read out in input order for each line, and repeatedly displayed on the display for every line. As a result, the sub-image can be displayed magnified by the above-mentioned specific scale factor in the horizontal and vertical directions. Therefore, only the sub-image data to be synthesized is stored in the frame memory, after which it is displayed magnified to the desired scale factor, so the capacity of the frame memory can be decreased, and it is possible to magnify to any scale factor, which allows the scale factor requirements of the user to be satisfied.
The fifth invention is the image synthesizing device according to any of first to four invention, wherein the selector 4 inputs the main image data that has undergone A/D conversion without going through a memory, switches it with the sub-image data to be synthesized, and outputs it for display on the display.
There is no need for a memory for storing the main image data used for image synthesis, and the main image data is switched with the sub-image data to be synthesized, which is outputted directly to the display, so the memory of the image data can be smaller.
The sixth invention is the image synthesizing device according to fourth invention, wherein the line buffer FIFO stores one line of the sub-image data read from the frame memory at a cycle reduced to the specific scale factor with respect to the frequency of the horizontal dot clock of the main image in the inputted order, after which one line of the stored sub-image data is read out at a cycle reduced to the specific scale factor with respect to the frequency of the horizontal dot clock of the main image in the inputted order for the remaining lines of the specific lines corresponding to the specific scale factor of the display region of the main image data, and is repeatedly outputted for each line.
Only that data corresponding to the display region where the sub-image data is to be synthesized is continuously written to the frame memory in input order, and then when the synthesis and display region of the main image data is displayed, the main image data is switched so that the stored sub-image data is synthesized and displayed while being magnified horizontally and vertically as follows. The display is magnified horizontally by reading out from the frame memory one line of the stored sub-image data at a cycle reduced to a specific magnification factor for the frequency of the horizontal synchronization signal of the main image one line at a time for a specific number of lines corresponding to the above-mentioned magnification factor. Along with this, this read sub-image data is written to the line buffer FIFO in full scale, that is, at a cycle reduced to the above-mentioned scale factor just as it was read out from the above-mentioned frame memory. Then, for the rest of the above-mentioned specific number of lines, the sub-image data is continuously read out in input order from this line buffer FIFO and displayed magnified at a cycle reduced to the above-mentioned scale factor for the frequency of the horizontal synchronization signal of the main image, and this is repeated for every line. As a result, the sub-image can be displayed magnified by the above-mentioned specific scale factor in both the horizontal and the vertical directions. Therefore, only the sub-image data to be synthesized is stored in the frame memory, after which it is displayed magnified to the desired scale factor, so the capacity of the frame memory can be decreased. Also, because it is stored still in full scale in the line buffer FIFO, and it is magnified to the specified scale factor during read-out, the memory capacity of the line buffer FIFO can also be decreased, which allows the scale factor requirements of the user to be satisfied.
The seventh invention is an image conversion device which converts interlaced scan image signals composed of odd-numbered fields and even-numbered fields into non-interlaced scan image signals, comprising: one frame memory with which write and read operations can be performed asynchronously and which stores inputted interlaced scan image signals; first write control means for storing image signals of the lines of one of the fields out of the interlaced scan image signals, corresponding to an order of the lines in the one field, in an intermittent address region in which an origin is a leading address of the frame memory emptied for each address region corresponding to one line of image data; second write control means for storing image signals of the lines of the other field out of the interlaced scan image signals, corresponding to an order of the lines in the other field, in empty address regions formed between the intermittent address regions of the frame memory; and read control means for reading, in an address order from the leading address, the interlaced signals stored in the order of non-interlaced scan lines in the continuous address region of the one frame memory by the first and second write control means; and wherein the interlaced signals are converted into non-interlaced signals through the one frame memory.
First, the interlaced image of one field is stored in alternating address regions of the frame memory, and then the interlaced image of the other field is stored in the empty regions between the above-mentioned alternating address regions, and as a result an interlaced image is stored in the line order of the non-interlaced scan in the continuous address region of the frame memory. Therefore, reading this stored image in the address order results in the interlaced signals being converted into non-interlaced signals. Therefore, with this invention, interlaced signals can be converted into non-interlaced signals using only a single frame memory, which reduces the cost of the device and is also advantageous in terms of mounting surface area.
The eight invention is an image conversion method in which interlaced scan image signals composed of odd-numbered fields and even-numbered fields are converted into non-interlaced scan image signals through one frame memory, comprising: a first step of storing image signals of lines of one of the fields out of the interlaced scan image signals, corresponding to an order of the lines in the one field, in an intermittent address region in which an origin is a leading address of the frame memory emptied for each address region corresponding to one line of image data; a second step of storing image signals of lines of the other field out of the interlaced scan image signals, corresponding to an order of lines in the other field, in empty address regions formed between the intermittent address regions of the frame memory; and a third step of reading, in an address order from the leading address, the interlaced signals stored in the one frame memory.
First, the interlaced image of one field is stored in alternating address regions of the frame memory, and then the interlaced image of the other field is stored in the empty regions between the above-mentioned alternating address regions, and as a result an interlaced image is stored in the line order of the non-interlaced scan in the continuous address region of the frame memory. Therefore, reading this stored image in the address order results in the interlaced signals being converted into non-interlaced signals. With this invention, interlaced signals can be converted into non-interlaced signals using only a single frame memory, which reduces the cost of the device and is also advantageous in terms of mounting surface area.
The ninth invention is an image conversion device which converts interlaced scan image signals composed of odd-numbered fields and even-numbered fields into non-interlaced scan image signals, comprising: one serial access memory with which write and read operations can be performed asynchronously and which sequentially stores interlaced scan image signals in an address region incremented synchronously with inputted clock signals; write clock formation means for extracting control-use synchronization signals from inputted interlaced scan image signals and forming write-use clock signals with respect to the serial access memory on the basis of the extracted signals; high-speed clock signal generation means for generating high-speed clock signals with a higher frequency than the write-use clock signals; first write control means for storing image data of one of the fields in an intermittent address region of the serial access memory corresponding to an order of lines in the one field by alternately executing a first operation, in which one line of interlaced scan image data is written while the write address of the serial access memory is incremented synchronously with the write-use clock signals when image data of one of the fields of the interlaced scan image signals has been inputted, and a second operation, in which the write address of the serial access memory is incremented by an amount equal to the address region corresponding to one line of image data synchronously with the high-speed clock signals without data writing being performed, with a leading address of the serial access memory serving as an origin; second write control means for storing, corresponding to an order of lines in the other field, image data of the other field in empty address regions formed between the address regions where the image of the lines of the one field of the serial access memory is stored by alternately executing a third operation, in which one line of interlaced scan image data is written while the write address of the serial access memory is incremented synchronously with the write-use clock signals when image data of the other field of the interlaced scan image signals has been inputted, and a fourth operation, in which the write address of the serial access memory is incremented by an amount equal to the address region corresponding to one line of image data synchronously with the high-speed clock signals without data writing being performed, with an address advanced by an address region corresponding to one line of image data from the leading address serving as the origin; and read control means for reading, in the address order from the leading address, the interlaced scan image data stored in the serial access memory by the first and second write control means; and wherein interlaced signals are converted into non-interlaced signals through the one serial access memory.
First, the required image data of one field of interlaced scan image signals is stored in alternating address regions of the serial access memory, and then the required image data of the other field is stored in the empty regions between the above-mentioned alternating address regions, and as a result interlaced scan image data is stored in the line order of the non-interlaced scan in the continuous address region of the serial access memory. Therefore, reading this stored image in the address order results in the interlaced signals being converted into non-interlaced signals. With this invention, one frame of interlaced image signals can be stored in a single serial access memory, which reduces the number of serial access memories to one and allows the memory storage region to be utilized more effectively.
The tenth invention is an image synthesizing device with which a sub-image included in a specific extraction region of an interlaced scan sub-image composed of odd-numbered fields and even-numbered fields is synthesized and displayed within a specific display region on a display screen on which a non-interlaced scan main image is displayed, comprising: one serial access memory with which write and read operations can be performed asynchronously and which sequentially stores sub-image signals in an address region which is advanced synchronously with inputted clock signals; write clock formation means for extracting control-use synchronization signals from inputted sub-image signals and forming write-use clock signals with respect to the serial access memory on the basis of the extracted signals; high-speed clock signal generation means for generating high-speed clock signals with a higher frequency than the write-use clock signals; first write control means for storing the image data to be displayed in the display region of one of the fields out of the sub-image signals in an intermittent address region of the serial access memory corresponding to an order of lines in the one field by alternately executing a first operation, in which one line of data to be displayed in the display region of the one field is written while the write address of the serial access memory is incremented synchronously with the write-use clock signals when an image of the one field has been inputted and when the sub-image included in the specific extraction region has been inputted, and a second operation, in which the write address of the serial access memory is incremented by an amount equal to the address region corresponding to one line of sub-image data to be displayed in the display region synchronously with the high-speed clock signals without data writing being performed, with a leading address of the serial access memory serving as an origin; second write control means for storing, corresponding to an order of lines in the other field out of the sub-image signals, the image data to be displayed in the display region of the other field in empty address regions formed between the address regions where the image of the lines of the one field of the serial access memory is stored by alternately executing a third operation, in which one line of data to be displayed in the display region of the other field is written while the write address of the serial access memory is incremented synchronously with the write-use clock signals when an image of the other field has been inputted and when the sub-image included in the specific extraction region has been inputted, and a fourth operation, in which the write address of the serial access memory is incremented by an amount equal to the address region corresponding to one line of sub-image data to be displayed in the display region synchronously with the high-speed clock signals without data writing being performed, with an origin address being an address advanced from the leading address by an amount equal to the address region corresponding to one line of image data to be displayed in the display region; read control means for reading, in the address order from the leading address, the sub-image data stored in the serial access memory by the first and second write control means when the scanning address of the main image is an address corresponding to the specific display region; and switching means for selecting the main image when the scanning address of the main image is not an address corresponding to the specific display region, and selecting and outputting the sub-image outputted from the serial access memory when the scanning address of the main image is an address corresponding to the specific display region.
In the course of the synthesis and display of a sub-image included in a specific extraction region out of interlaced scan sub-images composed of odd-numbered fields and even-numbered fields in a specific display region on a display screen on which a non-interlaced scan main image is displayed, first, the required image data of one field is stored in alternating address regions of the serial access memory, and then the required image data of the other field is stored in the empty regions between the above-mentioned alternating address regions, and as a result a sub-image is stored in the line order of the non-interlaced scan in the continuous address region of the serial access memory. Therefore, reading this stored sub-image in the address order, switch it to the main image, and outputting this to the display allows a sub-image to be synthesized with the main image. With this invention, one frame of interlaced image signals can be stored in a single serial access memory, which reduces the number of serial access memories to one and allows the memory storage region to be utilized more effectively. Also, because the interlaced image signals are stored in a continuous address region, when they are synthesized into a main image, the address control performed for this read-out is simpler.
The eleventh invention is such that a sub-image included in a specific extraction region out of an interlaced scan sub-image composed of odd-numbered fields and even-numbered fields will be reduced and displayed in part of the region on a display screen where a non-interlaced scan main image is displayed, and adds to the structure corresponding to fourth invention reduction factor setting means for setting a reduction factor of the sub-image; and display region setting means for setting a reduction of the display region in which the sub-image is displayed on the display screen according to the reduction factor set by the reduction factor setting means; wherein the first write control means, in a course of the execution of the first operation, thins the sub-image of one of the fields included in the specific extraction region in a main scanning direction and a sub-scanning direction according to the set reduction factor, and in a course of the execution of the second operation, increments the write address of the serial access memory by an amount equal to the address region corresponding to one line of reduced sub-image data to be displayed in the display region; the second write control means, in a course of the execution of the third operation, thins the sub-image of the other field included in the specific extraction region in the main scanning direction and the sub-scanning direction according to the set reduction factor, and in a course of the execution of the fourth operation, increments the write address of the serial access memory by an amount equal to the address region corresponding to one line of reduced sub-image data to be displayed in the display region, and alternately executes these third and fourth operations, with the origin being an address advanced from the leading address by an amount equal to the address region corresponding to one line of image data to be displayed in the display region; the read control means reads the sub-image data stored in the serial access memory by the first and second write control means in the address order from the leading address when the scanning address of the main image is an address corresponding to the display region reduced by the display region setting means; and the switching means selects the main image when the scanning address of the main image is not an address corresponding to the display region reduced by the display region setting means, and selects and outputs the sub-image outputted from the serial access memory when the scanning address of the main image is an address corresponding to the display region reduced by the display region setting means.
The timing at which data is written to the serial access memory is controlled according to the reduction factor, and as a result the sub-image of one field reduced according to the reduction factor is stored in alternating address regions of the serial access memory, and the sub-image of the other field reduced according to the reduction factor is stored in the empty spaces between the above-mentioned alternating address regions, and as a result, a reduced sub-image is stored in the order of the lines of the non-interlaced scan in the continuous address region of the serial access memory. Therefore, a reduced sub-image can be synthesized on the main image screen by reading out this stored sub-image in the address order, switching it to the main image, and displaying this on the display. Thus, with this invention, a reduced sub-image can be synthesized on the main screen using only a single serial access memory, which reduces the number of serial access memories to one and allows the memory storage region to be utilized more effectively. Also, because the reduced interlaced image signals are stored in a continuous address region, when they are synthesized into a main image, the address control performed for this read-out is simpler.
The twelfth invention is an image conversion device which converts interlaced scan image signals composed of odd-numbered fields and even-numbered fields into non-interlaced scan image signals, comprising: one video memory with which write and read operations can be performed asynchronously and which sequentially stores interlaced scan image signals in an address region corresponding to inputted address signals; first write control means for storing the image data of one of the fields in an intermittent address region of the video memory corresponding to an order of lines in the one field by alternately executing a first operation, in which one line of interlaced scan image data is written while the write address of the video memory is advanced when image data of one of the fields of the interlaced scan image signals has been inputted, and a second operation, in which the write address of the video memory is skipped by an amount equal to the address region corresponding to one line of image data without data writing being performed, with a leading address of the video memory serving as an origin; second write control means for storing, corresponding to an order of lines in the other field out of the sub-image signals, the image data of the other field in empty address regions formed between the address regions where the image of the lines of the one field of the video memory is stored by alternately executing a third operation, in which one line of interlaced scan image data is written while the write address of the video memory is advanced when an image of the other field has been inputted, and a fourth operation, in which the write address of the video memory is skipped by an amount equal to the address region corresponding to one line of image data without data writing being performed, with the origin being an address advanced from the leading address by an amount equal to the address region corresponding to one line of image data; and read control means for reading, in the address order from the leading address, the interlaced scan image data stored in the video memory by the first and second write control means; and wherein interlaced signals are converted into non-interlaced signals through the one video memory.
An ordinary video memory whose address regions are specified by ordinary addressing is used as the memory for storing the interlaced scan image. Specifically, first, the required image data of one field of interlaced scan image signals is stored in alternating address regions of the video memory, and then the required image data of the other field is stored in the empty regions between the above-mentioned alternating address regions, and as a result interlaced scan image data is stored in the line order of the non-interlaced scan in the continuous address region of the video memory. Therefore, reading this stored image data in the address order allows the interlaced signals to be converted into non-interlaced signals. Thus, with this invention, one frame of interlaced image signals can be stored in a single video memory, which reduces the number of video memories to one and allows the memory storage region to be utilized more effectively.
The thirteenth invention is an image synthesizing device with which a sub-image included in a specific extraction region of an interlaced scan sub-image composed of odd-numbered fields and even-numbered fields is synthesized and displayed within a specific display region on a display screen on which a non-interlaced scan main image is displayed, comprising: one video memory with which write and read operations can be performed asynchronously and which sequentially stores sub-image signals in an address region corresponding to inputted address signals; first write control means for storing the image data to be displayed in the display region of one of the fields out of the sub-image signals in an intermittent address region of the video memory corresponding to an order of lines in the one field by alternately executing a first operation, in which one line of data to be displayed in the display region of the one field is written while the write address of the video memory is advanced when an image of the one field has been inputted and when the sub-image included in the specific extraction region has been inputted, and a second operation, in which the write address of the video memory is skipped by an amount equal to the address region corresponding to one line of sub-image data to be displayed in the display region without data writing being performed, with a leading address of the video memory serving as an origin; second write control means for storing, corresponding to an order of lines in the other field out of the sub-image signals, the image data to be displayed in the display region of the other field in empty address regions formed between the address regions where the image of the lines of the one field of the video memory is stored by alternately executing a third operation, in which one line of data to be displayed in the display region of the other field is written while the write address of the video memory is advanced when an image of the other field has been inputted and when the sub-image included in the specific extraction region has been inputted, and a fourth operation, in which the write address of the video memory is skipped by an amount equal to the address region corresponding to one line of sub-image data to be displayed in the display region without data writing being performed, with the origin being an address advanced from the leading address by an amount equal to the address region corresponding to one line of image data to be displayed in the display region; read control means for reading, in the address order from the leading address, the sub-image data stored in the video memory by the first and second write control means when the scanning address of the main image is an address corresponding to the specific display region; and switching means for selecting the main image when the scanning address of the main image is not an address corresponding to the specific display region, and selecting and outputting the sub-image outputted from the video memory when the scanning address of the main image is an address corresponding to the specific display region.
An ordinary video memory whose address regions are specified by ordinary addressing is used as the memory for storing the interlaced scan image. Specifically, in the course of the synthesis and display of a sub-image included in a specific extraction region out of interlaced scan sub-images composed of odd-numbered fields and even-numbered fields in a specific display region on a display screen on which a non-interlaced scan main image is displayed, first, the required sub-image of one field is stored in alternating address regions of the video memory, and then the required sub-image of the other field is stored in the empty regions between the above-mentioned alternating address regions, and as a result the sub-image is stored in the line order of the non-interlaced scan in the continuous address region of the video memory. Therefore, reading this stored sub-image in the address order, switching it with the main image, and outputting it to the display allows the sub-image to be synthesized with the main image. Thus, with this invention, one frame of interlaced image signals can be stored in a single video memory, which reduces the number of video memories to one and allows the memory storage region to be utilized more effectively. Also, because the interlaced image signals are stored in a continuous address region, when they are synthesized into a main image, the address control performed for this read-out is simpler.
The fourteenth invention is the image synthesizing device according to thirteenth invention, further comprising reduction factor setting means for setting a reduction factor of the sub-image; and display region setting means for setting a reduction of the display region in which the sub-image is displayed on the display screen according to the reduction factor set by the reduction factor setting means; wherein the first write control means, in a course of the execution of the first operation, thins the sub-image of one of the fields included in the specific extraction region in a main scanning direction and a sub-scanning direction according to the set reduction factor, and in a course of the execution of the second operation, skips the write address of the video memory by an amount equal to the address region corresponding to one line of reduced sub-image data to be displayed in the display region; the second write control means, in a course of the execution of the third operation, thins the sub-image of the other field included in the specific extraction region in the main scanning direction and the sub-scanning direction according to the set reduction factor, and in a course of the execution of the fourth operation, skips the write address of the video memory by an amount equal to the address region corresponding to one line of reduced sub-image data to be displayed in the display region, and alternately executes these third and fourth operations, with the origin being an address advanced from the leading address by an amount equal to the address region corresponding to one line of image data to be displayed in the display region; the read control means reads the sub-image data stored in the video memory by the first and second write control means in the address order from the leading address when the scanning address of the main image is an address corresponding to the display region reduced by the display region setting means; and the switching means selects the main image when the scanning address of the main image is not an address corresponding to the display region reduced by the display region setting means, and selects and outputs the sub-image outputted from the video memory when the scanning address of the main image is an address corresponding to the reduced display region.
The timing at which data is written to the video memory is controlled according to the reduction factor, and as a result the sub-image of one field reduced according to the reduction factor is stored in alternating address regions of the serial access memory, and the sub-image of the other field reduced according to the reduction factor is stored in the empty spaces between the above-mentioned alternating address regions, and as a result, a reduced sub-image is stored in the order of the lines of the non-interlaced scan in the continuous address region of the video memory. Therefore, a reduced sub-image can be synthesized on the main image screen by reading out this stored sub-image in the address order, switching it to the main image, and displaying this on the display. Thus, with this invention, a reduced sub-image can be synthesized on the main screen using only a single video memory, which reduces the number of serial access memories to one and allows the memory storage region to be utilized more effectively. Also, because the reduced interlaced image signals are stored in a continuous address region, when they are synthesized into a main image, the address control performed for this read-out is simpler.
With the fifteenth invention the video memory according to fifteenth invention claim 13 comprises: random access memory means allowing write and read operations to be performed asynchronously and for sequentially storing sub-image signals written by the first and second write control means;
serial access memory means for temporarily storing at least one line of sub-image signals by data transfer from the random access memory means; and first read control means for performing data read control from the serial access memory means on the basis of inputted serial clock signals; read clock formation means is provided for extracting control-use synchronization signals from inputted main image signals and forming read-out clock signals with respect to the video memory on the basis of the extraction signals; the display screen on which the main image is displayed performing a display operation synchronously with the read clock signals;
magnification factor setting means is provided for setting the magnification factor M; and display region setting means is provided for setting the magnification of the display region in which the sub-image is displayed on the display screen according to a magnification factor M set by the magnification factor setting means; the read control means comprises: address generation means for generating addresses increased by an amount of address skipped by the first and second write control means once for every M-number of sub-scans of the main image, with an initial value being a leading address of the random access memory means; second read control means for causing the data transfer to be performed, with an output address of the address generation means being a transfer start address, at least once for every M-number of sub-scans of the main image when the sub-scanning address of the main image is an address corresponding to the display region magnified by the display region setting means; main scanning direction magnification means for forming serial clock signals obtained by dividing the read clock signals into 1/M according to the magnification factor, inputting the serial clock signals thus formed to the second read control means, and causing data corresponding to the amount of address skipped by the second write control means out of the sub-image signals stored temporarily in the serial access memory means to be outputted at a frequency of 1/M when the scanning address of the main image is an address corresponding to the display region magnified by the display region setting means; and sub-scanning direction magnification means for outputting the sub-image signals temporarily stored in the serial access memory means continuously for M times and synchronously with the sub-scanning of the main image when the scanning address of the main image is an address corresponding to the display region magnified by the display region setting means; and wherein the switching means selects the main image when the scanning address of the main image is not an address corresponding to the display region magnified by the display region setting means, and selects and outputs the sub-image outputted from the video memory when the scanning address of the main image is an address corresponding to the display region magnified by the display region setting means.
Since a magnified sub-image is superimposed over the main image using the serial access memory housed in an ordinary video memory, there is no need for the line buffer FIFO used in fourth and sixth, which allows the circuit structure to be that much simpler and the cost that much lower.